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low power hart modem data sheet ad5700 / ad5700-1 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features hart-compliant fully integrated fsk modem 1200 hz and 2200 hz sinusoidal shift frequencies 115 a maximum supply current in receive mode suitable for intrinsically safe applications integrated receive band-pass filter minimal external components required clocking optimized for various system configurations ultralow power crystal oscillator (60 a maximum) external cmos clock source precision internal oscillator ( ad5700-1 only) buffered hart outputextra drive capability 8 kv hbm esd rating 2 v to 5.5 v power supply 1.71 v to 5.5 v interface ?40c to +125c operation 4 mm 4 mm lfcsp package hart physical layer compliant uart interface applications field transmitters hart multiplexers plc and dcs analog i/o modules hart network connectivity general description the ad5700 / ad5700-1 are single-chip solutions, designed and specified to operate as a hart? fsk half-duplex modem, complying with the hart physical layer requirements. the ad5700/ ad5700-1 integrate all of the necessary filtering, signal detection, modulating, demodulating and signal generation functions, thus requiring few external components. the 0.5% precision internal oscillator on the ad5700-1 greatly reduces the board space requirements, making it ideal for line-powered applications in both master and slave configurations. the maxi- mum supply current consumption is 115 a, making the ad5700/ ad5700-1 an optimal choice for low power loop-powered applica- tions. transmit waveforms are phase continuous 1200 hz and 2200 hz sinusoids. the ad5700 / ad5700-1 contain accurate carrier detect circuitry and use a standard uart interface. table 1. related products part no. description ad5755-1 quad-channel, 16-bit, serial input, 4 ma to 20 ma and voltage output dac, dynamic power control, hart connectivity ad5421 16-bit, serial input, loop powered, 4 ma to 20 ma dac ad5410 / ad5420 single-channel, 12-bit/16-bit, serial input, 4 ma to 20 ma current source dacs AD5412 / ad5422 single-channel, 12-bit/16-bit, serial input, current source and voltage output dacs functional block diagram figure 1. osc xtal1 ref ref_en agnd dgnd filter_sel clkout reg_cap v cc reset cd duplex iov cc hart_out adc_ip hart_in rxd txd rts clk_cfg0 clk_cfg1 xtal_en ad5700/ad5700-1 xtal2 control logic 10435-001 fsk modulator voltage reference dac fsk demodulator band-pass filter and biasing adc buffer
ad5700/ad5700-1 data sheet rev. a | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 9 ? terminology .................................................................................... 12 ? theory of operation ...................................................................... 13 ? fsk modulator ........................................................................... 13 ? connecting to hart_out ..................................................... 14 ? fsk demodulator ...................................................................... 14 ? connecting to hart_in or adc_ip .................................... 14 ? clock configuration .................................................................. 15 ? power-down mode .................................................................... 16 ? full duplex operation ............................................................... 16 ? applications information .............................................................. 17 ? supply decoupling ..................................................................... 17 ? typical connection diagrams .................................................. 17 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 4/12rev. 0 to rev. a change to transmit impedance parameter, rts low, table 2 .. 4 changes to figure 3, figure 4, figure 5, and figure 7 ................. 9 changes to figure 10 and figure 11............................................. 10 changed ad5755 to ad5755-1 throughout ............................. 17 change to figure 27 ....................................................................... 18 2/12revision 0: initial version
data sheet ad5700/ad5700-1 rev. a | page 3 of 20 specifications v cc = 2 v to 5.5 v, iov cc = 1.71 v to 5.5 v, agnd = dgnd, clkout disabled, hart_out with 5 nf load, internal and external receive filter, internal reference, all specifications are from ?40c to +125c and relate to both a and b models, unless other wise noted. table 2. parameter 1 min typ max unit test conditions/comments power requirements 2 v cc 2 5.5 v iov cc 1.71 5.5 v v cc and iov cc current consumption demodulator 86 115 a b model, external clock, ?40c to +85c 179 a b model, external clock, ?40c to +125c 69 97 a b model, external clock, ?40c to +85c, external reference 157 a b model, external clock, ?40c to +125 c, external reference 260 a a model, external clock, ?40c to +125c modulator 124 140 a b model, external clock, ?40c to +85c 193 a b model, external clock, ?40c to +125c 73 96 a b model, external clock, ?40c to +85c, external reference 153 a b model, external clock, ?40c to +125c, external reference 270 a a model, external clock, ?40c to +125c crystal oscillator 3 33 60 a external crystal, 16 pf at xtal1 and xtal2 44 71 a external crystal, 36 pf at xtal1 and xtal2 internal oscillator 4 218 285 a ad5700-1 only, external crystal not required power-down mode reset = ref_en = dgnd v cc and iov cc current consumption 16 35 a internal reference disabled, ?40c to +85c 75 a internal reference disabled, ?40c to +125c internal voltage reference internal reference voltage 1.47 1.5 1.52 v ref_en = iov cc to enable use of internal reference load regulation 18 ppm/a tested with 50 a load optional external voltage reference external reference input voltage 2.47 2.5 2.53 v ref_en = dgnd to enable use of external reference, v cc = 2.7 v minimum external reference input current demodulator 16 21 a current required by external reference in receive mode modulator 28 33 a current required by external reference in transmit mode internal oscillator 5.5 7 a current required by external reference if using internal oscillator power-down 4.6 8.6 a digital inputs v ih , input high voltage 0.7 iov cc v v il , input low voltage 0.3 iov cc v input current ?0.1 +0.1 a input capacitance 5 5 pf per pin
ad5700/ad5700-1 data sheet rev. a | page 4 of 20 parameter 1 min typ max unit test conditions/comments digital outputs v oh , output high voltage iov cc ? 0.5 v v ol , output low voltage 0.4 v cd assert 6 85 100 110 mv p-p hart_in input 5 input voltage range 0 ref v external reference source 0 1.5 v internal reference enabled hart_out output output voltage 459 493 505 mv p-p ac-coupled (2.2 f), measured at hart_out pin with 160 load (worst-case load), see figure 15 and figure 16 for hart_out voltage vs. load mark frequency 7 1200 hz internal oscillator space frequency 7 2200 hz internal oscillator frequency error ?0.5 +0.5 % internal oscillator, ?40c to +85c ?1 +1 % internal oscillator, ?40c to +125c phase continuity error 5 0 degrees maximum load current 5 160 worst-case load is 160 , ac-coupled with 2.2 f, see figure 19 for recommended configuration if driving a resistive load transmit impedance 7 rts low, at the hart_out pin 70 k rts high, at the hart_out pin 1 temperature range: ?40c to +125c; typical at 25c. 2 current consumption sp ecifications are based on mean current values. 3 the demodulator and modulator currents are specified using an external clock. if using an external crystal oscillator, the cry stal oscillator current specification must be added to the corresponding v cc and iov cc demodulator/modulator current spec ification to obtain the total supp ly current required in this mode. 4 the demodulator and modulator currents are specified using an external clock. if using the internal oscillator, the internal o scillator current spec ification must be added to the corresponding v cc and iov cc demodulator/modulator current spec ification to obtain the total supp ly current required in this mode. 5 guaranteed by design and characterization, but not production tested. 6 specification set assuming a sinusoidal inpu t signal containing preamble characters at the input and an ideal external filter (see figure 21). 7 if the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.
data sheet ad5700/ad5700-1 rev. a | page 5 of 20 timing characteristics v cc = 2 v to 5.5 v, iov cc = 1.71 v to 5.5 v, t min to t max , unless otherwise noted, 1 bit time = 1/1200 hz = 833.333 s. table 3. parameter 1 limit at t min , t max unit description t 1 1 bit time 2 max carrier start time. time from rts falling edge to carrier reaching its first peak. see figure 3. t 2 1 bit time 2 max carrier stop time. time from rts rising edge to carrier amplitude dropping to ac zero. see figure 4. t 3 1 bit time 2 max carrier decay time. time from rts rising edge to carrier amplitude dropping to ac zero. see figure 4. t 4 6 bit times 2 max carrier detect on. time from carrier on to cd rising edge. see figure 5. t 5 6 bit times 2 max carrier detect off. time from carrier off to cd falling edge. see figure 6. t 6 10 bit times 2 max carrier detect on when switching from transmit mode to receive mode in the presence of a constant valid carrier. time from rts rising edge to cd rising edge. see figure 7. t 7 2.1 ms typ crystal oscillator power-up time. on application of a valid power supply voltage at v cc or on enabling of the oscillator via the xtal_en pin. crystal load capacitors = 8 pf. t 8 6 ms typ crystal oscillator power-up time. crystal load capacitors = 18 pf. t 9 25 s typ internal oscillator power-up time. on application of a valid power supply voltage at v cc or on enabling of the oscillator via the clk_cfg0 and clk_cfg1 pins. t 10 10 ms typ reference power-up time. t 11 30 s typ transition time from power-down mode to normal operating mode (external clock source, external reference). 1 specifications apply to ad5700/ ad5700-1 configured with internal or external receive filter. 2 bit time is the length of time to transfer one bit of data.
ad5700/ad5700-1 data sheet rev. a | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 4. parameter rating v cc to gnd ?0.3 v to +7 v iov cc to gnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to iov cc + 0.3 v or +7 v (whichever is less) digital output to dgnd ?0.3 v to iov cc + 0.3 v or +7 v (whichever is less) hart_out to agnd ?0.3 v to +2.5 v hart_in to agnd ?0.3 v to v cc + 0.3 v or +7 v (whichever is less) adc_ip ?0.3 v to v cc + 0.3 v or +7 v (whichever is less) agnd to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial ?40c to +125c storage temperature range ?65c to +150c junction temperature (t j max ) 150c power dissipation (t j max C t a )/ ja lead temperature, jedec industry standard soldering j-std-020 esd human body model (ansi/esda/jedec js-001-2010) 8 kv field induced charge model (jedec jesd22_c101e) 1.5 kv machine model (ansi/esd s5.2-2009) 400 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja jc unit 24-lead lfcsp 30 3 c/w esd caution
data sheet ad5700/ad5700-1 rev. a | page 7 of 20 pin configuration and fu nction descriptions figure 2. ad5700 / ad5700-1 pin configuration table 6. ad5700 / ad5700-1 pin function descriptions pin no. mnemonic description 1 xtal_en crystal oscillator circuit enable. a low state enables the crystal oscillator circuit, and an external crystal is required. a high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator ( ad5700-1 only) provides the clock source. this pin is used in conjunction with the clk_cfg0 and clk_cfg1 pins in configuring the required clock generation scheme. 2 clkout clock output. if using the crystal oscill ator or the internal rc oscillator, a clock output can be configured at the clkout pin. enabling the clock output consumes extra cu rrent to drive the load on this pin. see the clkout section for more details. 3 clk_cfg0 clock configuration control. see table 7. 4 clk_cfg1 clock configuration control. see table 7. 5 reset active low digital input. holding reset low places the ad5700/ ad5700-1 in power-down mode. a high state on reset returns the ad5700 / ad5700-1 to their power-on state. if not us ing this pin, tie this pin to iov cc . 6 cd carrier detectdigital output. a high on cd indicates a valid carrier is detected. 7 txd transmit datadigital input. data input to the modulator. 8 rts request to senddigital input. a high state enables the demodulator and disables the modulator. a low state enables the modulator and disables the demodulator. 9 duplex a high state on this pin enables full duplex operation. see the theory of operation section. a low state disables this feature. 10 rxd receive datauart interface digital data output. data output from the demodulator is accessed on this pin. 11 iov cc digital interface supply. digital threshold levels are referenced to the voltage applied to this pin. the applied voltage can be in the range of 1.71 v to 5.5 v. 12 dgnd digital circuitry ground reference connection. for typica l operation, it is recommended to connect this pin to agnd. 13 reg_cap capacitor connection for internal voltage regula tor. connect a 1 f capacitor from this pin to ground. 14 hart_out hart fsk signal output. see the fsk modula tor section and figure 26 for typical connections. 15 ref internal reference voltage output, or external 2.5 v refe rence voltage input. connect a 1 f capacitor from this pin to ground. when supplying an external reference, the v cc supply requires a minimum voltage of 2.7 v. 16 hart_in hart fsk signal. when using the internal filter, couple th e hart input signal into this pin using a 2.2 nf series capacitor. if using an external band-pass filter as shown in figure 21, do not connect to this pin. 17 adc_ip if using the internal band-pass filter, connect 680 pf to this pin. alternatively, this pin allows direct connection to the adc input, in which case an external band-pass fi lter network must be used, as shown in figure 21. 18 v cc power supply input. 2 v to 5.5 v can be applied to this pin. v cc should be decoupled to ground with low esr 10 f and 0.1 f capacitors (see the supply decoupling section). 19 agnd analog circuitry ground reference connection. 10435-002 n o t e s 1 . t h e e x p o s e d p a d d l e s h o u l d b e c o n n e c t e d t o a g n d o r d g n d , o r , a l t e r n a t i v e l y , i t c a n b e l e f t e l e c t r i c a l l y u n c o n n e c t e d . i t i s r e c o m m e n d e d t h a t t h e p a d d l e b e t h e r m a l l y c o n n e c t e d t o a c o p p e r p l a n e f o r e n h a n c e d t h e r m a l p e r f o r m a n c e . 2 1 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 c d r e s e t c l k _ c f g 1 c l k _ c f g 0 c l k o u t x t a l _ e n r e g _ c a p h a r t _ o u t r e f h a r t _ i n a d c _ i p v c c 8 9 1 0 1 1 7 r t s d u p l e x r x d i o v c c 1 2 d g n d t x d 2 0 1 9 2 1 x t a l 2 a g n d x t a l 1 2 2 d g n d 2 3 r e f _ e n 2 4 f i l t e r _ s e l ad5700/ ad5700-1 top view (not to scale)
ad5700/ad5700-1 data sheet rev. a | page 8 of 20 pin no. mnemonic description 20 xtal2 connection for external 3.6864 mhz crystal. do not connect to this pin if using the internal rc oscillator ( ad5700-1 only) or an external clock source. 21 xtal1 connection for external 3.6864 mhz crystal or external cloc k source input. tie this pin to ground if using the internal rc oscillator ( ad5700-1 only). 22 dgnd digital circuitry ground reference connection. for typica l operation, it is recommended to connect this pin to agnd. 23 ref_en reference enable. a high state enables the internal 1.5 v reference and buffer. a low state disables the internal reference and input buffer, and a buffered external 2.5 v re ference source must be applied at ref. if ref_en is tied low, v cc must be greater than 2.7 v. 24 filter_sel band-pass filter select. a high state enables the internal filter and the hart signal should be applied to the hart_in pin. a low state disables the internal filter and an external band-pass filter must then be connected at the adc_ip input pin. in this case, the hart si gnal should be applied to the adc_ip pin. epad agnd analog ground reference connection. for typical operation, it is recommended to connect this pin to agnd.
data sheet ad5700/ad5700-1 rev. a | page 9 of 20 typical performance characteristics figure 3. carrier start time figure 4. carrier stop/decay time figure 5. carrier detect on timing figure 6. carrier detect off timing figure 7. carrier detect on when switching from transmit mode to receive mode in the presence of a constant valid carrier figure 8. supply currents vs. supply voltageexternal reference 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 time (ms) hart_out (v) 10435-003 txd rts t a = 25c; v cc = iov cc = 3.3v; int v ref rts and txd dc levels have been adjusted for clarity. in reality, both of these signals range from 0v to 3.3v. hart_out 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 time (ms) hart_out (v) 10435-004 txd rts hart_out t a = 25c; v cc = iov cc = 3.3v; int v ref rts and txd dc levels have been adjusted for clarity. in reality, both of these signals range from 0v to 3.3v. 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.5 0 0.5 1.0 1.5 2.0 2.5 time (ms) hart signal (v) 10435-005 rxd cd hart signal t a = 25c; v cc = iov cc = 3.3v; int v ref cd and rxd dc levels have been adjusted for clarity. in reality, both of these signals range from 0v to 3.3v. 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?5 ?4 ?3 ?2 ?1 0 1 time (ms) hart signal (v) 10435-006 rxd cd hart signal t a = 25c; v cc = iov cc = 3.3v; int v ref cd and rxd dc levels have been adjusted for clarity. in reality, both of these signals range from 0v to 3.3v. 1.50 1.25 1.00 0.75 0.50 0.25 0 ?0.50 ?0.25 ?0.75 ?1.00 ?10 ?7.5 ?5.0 ?2.5 0 2.5 time (ms) hart_out (v) 10435-007 cd hart_out hart signal rts t a = 25c; v cc = iov cc = 3.3v; int v ref rts and cd dc levels have been adjusted for clarity. in reality, both of these signals range from 0v to 3.3v. hart signal has also been offset by ?0.6v. 100 90 80 70 60 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc = iov cc (v) supply current (a) 10435-008 t a = 25c v cc = iov cc = 2.7v to 5.5v dev 1 ext ref demod i cc and ioi cc demod i ref mod i ref mod i cc and ioi cc
ad5700/ad5700-1 data sheet rev. a | page 10 of 20 figure 9. supply currents vs. supply voltageinternal reference figure 10. current in tx mode vs. resistive load figure 11. current in tx mode vs. capacitive load figure 12. input filter frequency response figure 13. reference voltage vs. v cc figure 14. reference voltage vs. temperature 200 180 160 140 120 100 80 60 40 20 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc = iov cc (v) i cc and ioi cc (a) 10435-026 t a = 25c v cc = iov cc = 2v to 5.5v dev 1 int ref demod i cc and ioi cc mod i cc and ioi cc 700 600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 r load ( ? ) with 22nf to gnd i cc current (a) 10435-009 hart_out 2.2f 22nf r load txd = 1 txd = 0 t a = 25c; v cc = iov cc = 3.3v; int v ref clk config = xtal oscillator ioi cc = 41a 250 225 200 175 150 125 100 75 50 25 0 0 102030405060 c load (nf) i cc current (a) 10435-010 t a = 25c; v cc = iov cc = 3.3v; int v ref clk config = xtal oscillator capacitive load only ioi cc = 41a txd = 1 txd = 0 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?20 ?18 100 1k 10k frequency (hz) gain (db) 10435-011 external filter internal filter t a = 25c v cc = iov cc = 3.3v int v ref 1.5012 1.5010 1.5008 1.5006 1.5004 1.5002 1.5000 1.4998 1.4996 1.01.52.02.53.03.54.04.55.05.56.0 v cc (v) v ref internal (v) 10435-012 t a = 25c v cc = iov cc = 2v to 5.5v 1.5006 1.5004 1.5002 1.5000 1.4998 1.4996 1.4994 1.4992 1.4990 ?40 ?20 0 20 40 60 80 100 120 temperature (c) v ref internal (v) 10435-013 v cc = iov cc = 2.7v temperature = ?40c to +125c
data sheet ad5700/ad5700-1 rev. a | page 11 of 20 figure 15. hart_out voltage vs. r load figure 16. hart_out voltage vs. c load 500 495 490 485 480 475 470 465 0 200 400 600 800 1000 1200 r load ( ? ) || with 22nf to gnd hart_out (mv p-p) 10435-014 hart_out 2.2f 22nf r load 1200hz 2200hz t a = 25c v cc = iov cc = 3.3v int v ref 505 501 502 503 504 500 499 498 497 496 495 0 102030405060 c load (nf) hart_out (mv p-p) 10435-015 1200hz 2200hz t a = 25c v cc = iov cc = 3.3v int v ref capacitive load only
ad5700/ad5700-1 data sheet rev. a | page 12 of 20 terminology v cc and iov cc current consumption this specification gives a summation of the current consump- tion of both the v cc and the iov cc supplies. figure 11 shows separate measurements for v cc and iov cc currents vs. varying capacitive loads, in transmit mode. load regulation load regulation is the change in reference output voltage due to a specified change in load current. it is expressed in ppm/a. cd assert the minimum value at which the carrier detect signal asserts is 85 mv p-p and the maximum value it asserts at is 110 mv p-p. cd is already high (asserted) for hart input signals greater than 110 mv p-p. this specification was set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see figure 21). hart_out output voltage this is the peak-to-peak hart_out output voltage. the specification in table 2 was set using a worst-case load of 160 , ac-coupled with a 2.2 f capacitor. figure 15 and figure 16 show hart_out output voltages for both resistive and purely capacitive loads. mark/space frequency a 1.2 khz signal represents a digital 1, or mark, whereas a 2.2 khz signal represents a 0, or space. phase continuity error the dds engine in this design inherently generates continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. this attribute is desirable for signals that are to be transmitted over a band limited channel, because discontinuities in a signal introduce wideband fre- quency components. as the name suggests, for a signal to be continuous, the phase continuity error must be 0 o .
data sheet ad5700/ad5700-1 rev. a | page 13 of 20 theory of operation highway addressable remote transducer (hart) communica- tion is the global standard for sending and receiving digital information across analog wires between smart field devices and control systems. this is a digital two-way communication system, in which a 1 ma p-p frequency shift keyed (fsk) signal is modulated on top of a 4 ma to 20 ma analog current signal. the ad5700 / ad5700-1 are designed and specified to operate as a single-chip, low power, hart fsk half-duplex modem, complying with the hart physical layer requirements (revision 8.1). a single-chip solution, the ad5700 / ad5700-1 not only inte- grate the modulation and demodulation functions, but also contain an internal reference, an integrated receive band-pass filter (which has the flexibility of being bypassed if required), and an internally buffered hart output, giving a high output drive capability and removing the need for external buffering. the ad5700-1 option also contains a precision internal rc oscillator. the block diagram in figure 1 shows a graphical illustration of how these circuit blocks are connected together. as a result of such extensive integration options, minimal external components are required. the ad5700 / ad5700-1 are suitable for use in both hart field instrument and master configurations. the ad5700 / ad5700-1 either transmit or receive 1.2 khz and 2.2 khz carrier signals. a 1.2 khz signal represents a digital 1, or mark, whereas a 2.2 khz signal represents a 0, or space. there are three main clocking configurations supported by these parts, two of which are available on the ad5700 option, whereas all three are available on the ad5700-1 device: ? external crystal ? cmos clock input ? internal rc oscillator ( ad5700-1 only) the device is controlled via a standard uart interface. the relevant signals are rts , cd, txd, and rxd (see table 6 for more detail on individual pin descriptions). fsk modulator the modulator converts a bit stream of uart-encoded hart data at the txd input to a sequence of 1200 hz and 2200 hz tones (see figure 17). this sinusoidal signal is internally buff- ered and output on the hart_out pin. the modulator is enabled by bringing the rts signal low. figure 17. ad5700 / ad5700-1 modulator waveform the modulator block contains a dds engine that produces a 1.2 khz or 2.2 khz sine wave in digital form and then performs a digital-to-analog conversion. this dds engine inherently generates continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. for more information on dds fundamentals, see mt-085 , fundamentals of direct digital synthesizers (dds) . figure 18 demonstrates a simple implementation of this fsk encoding. figure 18. dds-ba sed fsk encoder 10435-016 stop start 8-bit data + parity txd hart_out "1" = mark 1.2khz "0" = space 2.2khz 10435-017 1.2khz word 2.2khz word mux dds dac fsk 0 data 1 clock
ad5700/ad5700-1 data sheet rev. a | page 14 of 20 connecting to hart_out the hart_out pin is dc biased to 0.75 v and should be capacitively coupled to the load. the current consumption specifications in table 2 are based on driving a 5 nf load. if the application requires a larger load value, more current is required. this value can be calculated from the following formula: rms load ad5700 total iii ?? 2 2 2 1 24 mv500 load load rmsload r cf i ? ? ? ? ? ? ? ? ? ?? ? ? ? (1) where: i ad5700 is the current drawn by the ad5700/ ad5700-1 in transmit mode as per specifications (see table 2). note that the specifications in table 2 assume a 5 nf c load . f is the output frequency (1.2 khz or 2.2 khz). c load is the capacitive load to ground on hart_out. r load is the resistive load on the loop. when driving a purely capacitive load, the load should be in the range of 5 nf to 52 nf. see figure 11 for a typical plot of supply current vs. capacitive load. example assume use of an internal reference, and c load = 52 nf. i cc + ioi cc = 140 a maximum (from table 2 specification) note that this is incorporating a 5 nf load. therefore, to calculate the load current required to drive the extra 47 nf, use the equation 1. substituting f = 1200 hz, c load = 47 nf, and r load = 0 into the formula results in i load of 62.6 a. if using the crystal oscillator, this adds 60 a maximum (see table 2 for conditions). thus, the total worst-case current in this example is: 140 a + 62.6 a + 60 a = 262.6 a if driving a load with a resistive element, it is recommended to place a 22 nf capacitor to ground at the hart_out pin. the load should be coupled with a 2.2 f series capacitor. for low impedance devices, the r load range is typically 230 to 600 . figure 19. ad5700 / ad5700-1 with resistive load at hart_out fsk demodulator figure 20. ad5700 / ad5700-1 demodulator waveform (preamble message 0xff) when rts is logic high, the modulator is disabled and the demodulator is enabled, that is, the ad5700 / ad5700-1 are in receive mode. a high on cd indicates a valid carrier is detected. the demodulator accepts an fsk signal at the hart_in pin and restores the original modulated signal at the uart interface digital data output pin, rxd. the combination of the adc, digital filtering and digital demodulation results in a highly accurate output on the rxd pin. the hart bit stream follows a standard uart frame with a start bit, 8-bit data, one parity, and a stop bit (see figure 20). connecting to hart_in or adc_ip the ad5700 / ad5700-1 have two filter configuration options: an external filter (hart signal is applied to acp_ip) and an internal filter (hart signal is applied to hart_in). the external filter configuration is shown in figure 21. in this case, the hart signal is applied to the adc_ip pin through an external filter circuit. in safety critical applications, the ad5700/ ad5700-1 must be isolated from the high voltage of the loop supply. the recommended external band-pass filter includes a 150 k resistor, which limits current to a sufficiently low level to adhere to intrinsic safety requirements. in this case, the input has higher transient voltage protection and should, therefore, not require additional protection circuitry, even in the most demanding of industrial environments. assuming the use of a 1% accurate resistor and 10% accurate capacitor components, the calculated variation in cd trip voltage levels vs. the ideal is 3.5 mv. figure 21. ad5700 / ad5700-1 with external filter on adc_ip 10435-018 hart_out 2.2f 22nf r load 10435-019 stop start 8-bit data + parity rxd hart_in 10435-020 hart network 150k? 1.2m ? 1f 1.2m ? 300pf 150pf hart_out ref adc_ip ad5700/ ad5700-1
data sheet ad5700/ad5700-1 rev. a | page 15 of 20 the internal filter configuration is shown in figure 22. this option is beneficial where cost or board space is a large concern because it removes the need for multiple external components. this configuration achieves an 8 kv esd hbm rating but requires extra external protection circuitry for emc and surge protection purposes if used in harsh industrial environments. figure 22. ad5700 / ad5700-1 using internal filter on hart_in clock configuration the ad5700 / ad5700-1 support numerous clocking configura- tions to allow the optimal trade-off between cost and power: ? external crystal ? cmos clock input ? internal rc oscillator ( ad5700-1 only) the clk_cfg0, clk_cfg1, and xtal_en pins configure the clock generation as shown in table 7. the ad5700/ ad5700-1 can also provide a clock output at clkout (for more details, see the clkout section). external crystal the typical connection for an external crystal (abls-3.6864mhz- l4q-t) is shown in figure 23. to ensure minimum current consumption and to minimize stray capacitances, connections between the crystal, capacitors, and ground should be made as close to the ad5700/ ad5700-1 as possible. consult individual crystal vendors for recommended load information and crystal performance specifications. figure 23. crystal oscillator connection the abls-3.6864mhz-l4q-t crystal oscillator data sheet recommended two 18 pf capacitors. because the crystal current consumption is dominated by the load capacitance, in an effort to reduce the crystal current consumption, two 8 pf capacitors were used on the xtal1 and xtal2 pins. the ad5700/ ad5700-1 still functioned as expected, even with the resulting reduction in frequency performance from the crystal due to the smaller capacitance values. crystals are available that support 8 pf capacitors. it is recommended to consult the relevant crystal manufacturers for this information. cmos clock input a cmos clock input can also be used to generate a clock for the ad5700/ ad5700-1 . to use this mode, connect an external clock source to the xtal 1 pin, and leave xtal2 open circuit (see figure 24). figure 24. cmos clock connection internal oscillator ( ad5700-1 only) consuming typically 218 a, the low power, internal, 0.5 % precision rc oscillator, available only on the ad5700-1 , has an oscillation frequency of 1.2288 mhz. to use this mode, tie the xtal1 pin to ground and leave the xtal2 pin open circuit (see figure 25). figure 25. internal oscillator connection clkout the ad5700 / ad5700-1 can provide a clock output at clkout (see table 7). ? if using the crystal oscillator, this clock output can be configured as a 3.6864 mhz, 1.8432 mhz, or 1.2288 mhz buffer clock. ? if using a cmos clock, no clock output can be configured at the clkout pin. ? if using the internal rc oscillator, this clock output is only available as a 1.2288 mhz buffer clock. the amplitude of the clock output depends on the iov cc level; therefore, the clock output can be in the range of 1.71 v p-p to 5.5 v p-p. enabling the clock output of the ad5700/ ad5700-1 increases the current consumption of the device. this increase is due to the current required to drive any load at the clkout pin, which should not be more than 30 pf. this capacitance should be minimized to reduce current consumption and provide the clock with the cleanest edges. the additional current drawn from the iov cc supply can be calculated using the following equation: i = c v f 10435-021 hart network 680pf 2.2nf hart_out hart_in adc_ip ad5700/ ad5700-1 10435-022 abls-3-6864mhz-l4q-t 18pf 18pf xtal1 xtal2 ad5700/ad5700-1 10435-027 xtal1 xtal2 ad5700/ad5700-1 10435-028 xtal1 xtal2 ad5700-1
ad5700/ad5700-1 data sheet rev. a | page 16 of 20 table 7. clock configuration options xtal_en clk_cfg1 clk_cfg0 clkout description 1 0 0 no output 3.6864 mhz cmos clock connected at xtal1 pin 1 0 1 no output 1.2288 mhz cmos clock connected at xtal1 pin 1 1 0 no output internal oscillator enabled ( ad5700-1 only) 1 1 1 1.2288 mhz output internal oscillator enabled, clkout enabled ( ad5700-1 only) 0 0 0 no output crystal oscillator enabled 0 0 1 3.6864 mhz output crystal oscillator enabled, clkout enabled 0 1 0 1.8432 mhz output crystal oscillator enabled, clkout enabled 0 1 1 1.2288 mhz output crystal oscillator enabled, clkout enabled power-down mode the ad5700 / ad5700-1 can be placed into power-down mode by holding the reset pin low. if using the internal reference, it is recommended to tie the ref_en pin to the reset pin so that it is also powered down. if the reference is not powered down while reset is low, the output voltage on the ref pin is approximately 1.7 v until reset is brought high again. in this mode, the receive, transmit, and oscillator circuits are all switched off, and the device consumes a typical current of 16 a. full duplex operation full duplex operation means that the modulator and demodula- tor of the ad5700 / ad5700-1 are enabled at the same time. this is a powerful feature, enabling a self-test procedure of not only the hart device but also the complete signal path between the hart device and the host controller. this provides verification that the local communications loop is functional. this increased level of system diagnostics is useful in production self-test and is advantageous in improving the applications safety integrity level (sil) rating. the full duplex mode of operation is enabled by connecting the duplex pin to logic high.
data sheet ad5700/ad5700-1 rev. a | page 17 of 20 applications information supply decoupling it is recommended to decouple the v cc and iov cc supplies with 10 f in parallel with 0.1 f capacitors to ground. for many applications, 1 f in parallel with 0.1 f ceramic capacitors to ground should be sufficient. the reg_cap voltage of 1.8 v is used to supply the ad5700/ ad5700-1 internal circuitry and is derived from the v cc supply using a high efficiency clocking ldo. decouple this reg_cap supply with a 1 f ceramic capacitor to ground. it is also required to decouple the ref pin with a 1 f ceramic capacitor to ground. place decoupling capacitors as close to the relevant pins as possible. for loop-powered applications, it is recommended to connect a resistance in series with the v cc supply to minimize the effect of any noise, which may, depending on the system configuration, be introduced onto the loop as a result of current draw variations from the ad5700 / ad5700-1 . for typical applications, 470 of resistance has proven most effective. however, depending on the application conditions, alternative values may also be acceptable (see r1 in figure 27). typical connection diagrams figure 26 shows a typical connection diagram for the ad5700/ ad5700-1 using the external and internal options. see the connecting to hart_in or adc_ip section for more details. the ad5700 / ad5700-1 are designed to interface easily with analog devices, inc., innovative portfolio of industrial converters like the ad5421 loop-powered current-output dac, the ad5410 / ad5420 and AD5412/ ad5422 family of line- powered current-output dacs, and the ad5755-1 , a quad dac with innovative dynamic power control technology. the combination of analog devices industrial converters and the ad5700/ ad5700-1 greatly simplifies system design, enhancing reliability while reducing overall pcb size. figure 27 shows how the ad5700 / ad5700-1 hart modem can be interfaced with the ad5421 (4 ma to 20 ma loop-powered dac) and a microcontroller to construct a loop powered transmit- ter circuit. the hart signal from hart_out is introduced to the ad5421 via the c in pin. the hart enabled smart transmitter reference demo circuit (the block diagram shown in figure 28) was developed by analog devices and uses the ad5421 , a 16-bit, loop-powered, 4 ma to 20 ma dac, and the ad5700 modem. this circuit has been compliance tested, verified, and registered as an approved hart solution by the hart communication foundation. contact your sales representative for further information about this demo circuit. in conclusion, the ad5700/ ad5700-1 enable quick and easy deployment of a robust hart-compliant system. figure 26. ad5700 / ad5700-1 typical connection diagram for external and internal filter options 10435-023 10f 0.1f 0.1f 1f 10f 150pf 1f 2v to 5.5v 1.71v to 5.5v reg_cap reset iov cc v cc agnd ad5700/ad5700-1 clkout xtal1 xtal2 + 150k ? 1.2m ? 1.2m ? 300pf ref hart_out dgnd configuration pins ref_en filter_sel duplex clk_cfg0 clk_cfg1 xtal_en hart_in adc_ip cd rxd txd rts aduc7060 microcontroller 10f 0.1f 1f hart network hart network 2v to 5.5v reg_cap reset iov cc v cc agnd ad5700/ad5700-1 clkout xtal1 xtal2 + ref hart_out dgnd configuration pins ref_en filter_sel duplex clk_cfg0 clk_cfg1 xtal_en hart_in adc_ip cd rxd txd rts aduc7060 microcontroller 680pf 2.2nf 1f + 0.1f 10f 1.71v to 5.5v +
ad5700/ad5700-1 data sheet rev. a | page 18 of 20 figure 27. loop-powered transmitter diagram 10435-025 hart_out adc_ip ref ad5700/ad5700-1 47nf 168nf 300pf gnd v cc r l 200k ? loop? r ext1 r ext2 drive com refout1 refin reg_sel0 reg_sel1 reg_sel2 reg in iodv dd dv dd reg out v loop ad5421 19m ? 1m ? v loop mcu sync sclk sdin sdo r int /r ext alarm_current_direction range1 range0 fault ldac com txd rxd rts cd r1 r1 470 ? 1.2m ? 150k ? 1.2m ? 150pf optional resistor t1 optional mosfet dn2540 bsp129 0.1f sets regulator voltage c in 10f 0.1f 1f 0.1f v z = 4.7v 4.7f refout2 optional emc filter 1f
data sheet ad5700/ad5700-1 rev. a | page 19 of 20 figure 28. block diagramanalog devices hart-enabled smart transmitter reference demo circuit 10435-029 adc 0 pressure sensor simulation temperature sensor pt100 3.3v adc 1 adc dac mcu sram flash clock reset watchdog t1: cd t2: rts t3: com t4: test spi uart ad5700 ad5421 com v cc hart_out ref adc_ip 3.3v 3.3v v dd c in c_hart c_slew hart input filter com v-regulator temperature sensor com reg in v loop loop? test connector + ? 50 ? hart modem micro- controller watchdog timer lexc
ad5700/ad5700-1 data sheet rev. a | page 20 of 20 outline dimensions figure 29. 24-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very thin quad (cp-24-10) dimensions shown in millimeters ordering guide model 1 temperature range oscillator options receive supply current package description package option ad5700bcpz-r5 ?40c to +125c external clock, crystal 157 a 24-lead lfcsp_wq cp-24-10 ad5700bcpz-rl7 ?40c to +125c external clock, crystal 157 a 24-lead lfcsp_wq cp-24-10 ad5700acpz-rl7 ?40c to +125c external clock, crystal 260 a 24-lead lfcsp_wq cp-24-10 ad5700-1bcpz-r5 ?40c to +125c external clock, crystal or internal oscillator 442 a 24-lead lfcsp_wq cp-24-10 ad5700-1bcpz-rl7 ?40c to +125c external clock, crystal or internal oscillator 442 a 24-lead lfcsp_wq cp-24-10 ad5700-1acpz-rl7 ?40c to +125c external clock, crystal or internal oscillator 540 a 24-lead lfcsp_wq cp-24-10 eval-ad5700-1ebz evaluation board for ad5700 and ad5700-1 1 z = rohs compliant part. 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd-8. 072809a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 2.20 2.10 sq 2.00 ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10435-0-3/12(a)

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